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A hybrid element method for capacitance extraction in VLSI layout verification system

Author(s): E.B. Nowacka & N.P. vd. Meijs Abstract: In this paper we describe a hybrid element method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate circuit models for lay- out dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC's). We present a stand-alone extraction program which we developed for validation and testing purposes. We show that the hybrid method can be included in our VLSI layout verification package Space. 1 Introduction Parasitic interconnect capacitances in integrated circuits (IC's) are playing an increas- ingly significant role in the circuit's performance. Therefore, designers of modern IC's rely heavily on lay out-to-circuit extraction systems, which produce an equivalent elec... Pages: 10 Size: 779 kb Paper DOI: 10.2495/ES960141

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Download the Full Article This article is part of the WIT OpenView scheme and you can download the full text Adobe PDF article for FREE by clicking the 'Openview' icon to the right.